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"P-channel logic 2 T eDRAM macro with high retention bit architecture."

Sivasundar Manisankar, Yeonbae Chung (2018)

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DOI: 10.1002/CTA.2496

access: closed

type: Journal Article

metadata version: 2021-10-14

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Sivasundar Manisankar, Yeonbae Chung:
P-channel logic 2 T eDRAM macro with high retention bit architecture. Int. J. Circuit Theory Appl. 46(7): 1416-1425 (2018)

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