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"Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies."

Hirotaka Tamura et al. (2006)

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DOI: 10.1093/IETELE/E89-C.3.300

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/TamuraKYKGIO06
Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa:
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. IEICE Trans. Electron. 89-C(3): 300-313 (2006)

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