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"An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology."

Tetsuro Matsuno et al. (2010)

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DOI: 10.1587/TRANSELE.E93.C.820

access: closed

type: Journal Article

metadata version: 2020-04-11

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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/MatsunoFKHTSN10
Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. IEICE Trans. Electron. 93-C(6): 820-826 (2010)

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