"Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per ..."

Chizu Matsumoto et al. (2013)

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DOI: 10.1587/TRANSELE.E96.C.108

access: closed

type: Journal Article

metadata version: 2020-04-11

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Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko:
Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs. IEICE Trans. Electron. 96-C(1): 108-114 (2013)

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