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"Testable Design of Reversible Circuits Using Parity Preserving Gates."

Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar (2018)

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DOI: 10.1109/MDAT.2017.2771202

access: closed

type: Journal Article

metadata version: 2022-07-14

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  - journals/dt/GaurSG18
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  - https://dblp.org/rec/journals/dt/GaurSG18
Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar:
Testable Design of Reversible Circuits Using Parity Preserving Gates. IEEE Des. Test 35(4): 56-64 (2018)

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