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"Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan ..."

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti (2007)

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DOI: 10.1109/VLSID.2007.136

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design 2007: 351-356

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