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"A 4fJ/bit delay-hardened physically unclonable function circuit with ..."

Sanu Mathew et al. (2016)

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DOI: 10.1109/VLSIC.2016.7573554

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-25

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Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De:
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2

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