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"A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR."

Takato Katayama et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502298

access: closed

type: Conference or Workshop Paper

metadata version: 2018-10-30

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  - conf/vlsic/KatayamaMSH18
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Takato Katayama, Shiko Miyashita, Kazuki Sobue, Koichi Hamashita:
A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR. VLSI Circuits 2018: 205-206

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