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"4×4-bit array two phase clocked adiabatic static CMOS logic ..."

Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine (2010)

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DOI: 10.1109/VLSISOC.2010.5642688

access: closed

type: Conference or Workshop Paper

metadata version: 2019-12-27

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Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine:
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. VLSI-SoC 2010: 364-368

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