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"STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design."

Avik Bose, Prasun Ghosal, Saraju P. Mohanty (2016)

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DOI: 10.1109/ISVLSI.2016.127

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/isvlsi/BoseGM16
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  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/BoseGM16
Avik Bose, Prasun Ghosal, Saraju P. Mohanty:
STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design. ISVLSI 2016: 496-501

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