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"A double data rate 8T-cell SRAM architecture for systems-on-chip."

Saleh Abdel-Hafeez, Mohammad Shatnawi, Ann Gordon-Ross (2012)

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DOI: 10.1109/ISSOC.2012.6376347

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

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  dblp key:
  - conf/issoc/Abdel-HafeezSG12
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  - https://dblp.org/rec/conf/issoc/Abdel-HafeezSG12
Saleh Abdel-Hafeez, Mohammad Shatnawi, Ann Gordon-Ross:
A double data rate 8T-cell SRAM architecture for systems-on-chip. ISSoC 2012: 1-4

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