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"Design benchmarking to 7nm with FinFET predictive technology models."

Saurabh Sinha et al. (2012)

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DOI: 10.1145/2333660.2333666

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-09

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  dblp key:
  - conf/islped/SinhaCYCC12
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  - https://dblp.org/rec/conf/islped/SinhaCYCC12
Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao:
Design benchmarking to 7nm with FinFET predictive technology models. ISLPED 2012: 15-20

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