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"The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with ..."

Yusuhiro Sugimoto, Shigeo Imai (1999)

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DOI: 10.1109/ISCAS.1999.780636

access: closed

type: Conference or Workshop Paper

metadata version: 2019-02-19

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  dblp key:
  - conf/iscas/SugimotoI99
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  - https://dblp.org/rec/conf/iscas/SugimotoI99
Yusuhiro Sugimoto, Shigeo Imai:
The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with 10-bit linearity. ISCAS (2) 1999: 132-135

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