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"Efficient Thermal Via Planning for Placement of 3D Integrated Circuits."

Jing Li, Hiroshi Miyashita (2007)

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DOI: 10.1109/ISCAS.2007.378242

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Jing Li, Hiroshi Miyashita:
Efficient Thermal Via Planning for Placement of 3D Integrated Circuits. ISCAS 2007: 145-148

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