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"Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory ..."

Barry J. O'Sullivan et al. (2019)

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DOI: 10.1109/IRPS.2019.8720598

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  - conf/irps/OSullivanRRWLRC19
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Barry J. O'Sullivan, Romain Ritzenthaler, Gerhard Rzepa, Z. Wu, E. Dentoni Litta, O. Richard, T. Conard, V. Machkaoutsan, Pierre Fazan, C. Kim, Jacopo Franco, Ben Kaczer, Tibor Grasser, Alessio Spessot, Dimitri Linten, N. Horiguchi:
Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices. IRPS 2019: 1-8

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