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"Reducing latency times by accelerated routing mechanisms for an FPGA ..."

Oliver Sander et al. (2008)

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DOI: 10.1109/FPT.2008.4762371

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-28

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Oliver Sander, Michael Hübner, Jürgen Becker, Matthias Traub:
Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain. FPT 2008: 97-104

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