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"Optimizing streaming stencil time-step designs via FPGA floorplanning."

Marco Rabozzi et al. (2017)

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DOI: 10.23919/FPL.2017.8056764

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-24

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  dblp key:
  - conf/fpl/RabozziNFMS17
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  - https://dblp.org/rec/conf/fpl/RabozziNFMS17
Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio:
Optimizing streaming stencil time-step designs via FPGA floorplanning. FPL 2017: 1-4

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