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ORCID"Testable Clock Routing Architecture for Field Programmable Gate Arrays."
L. Kalyan Kumar et al. (2003)
- L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti:
Testable Clock Routing Architecture for Field Programmable Gate Arrays. FPL 2003: 1044-1047
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