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"FPGA acceleration of SAT/Max-SAT solving using variable-way cache."

Kenji Kanazawa, Tsutomu Maruyama (2014)

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DOI: 10.1109/FPL.2014.6927405

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  dblp key:
  - conf/fpl/KanazawaM14
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  - https://dblp.org/rec/conf/fpl/KanazawaM14
Kenji Kanazawa, Tsutomu Maruyama:
FPGA acceleration of SAT/Max-SAT solving using variable-way cache. FPL 2014: 1-4

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