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"Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency ..."

Alexandre F. Tenca, Milos D. Ercegovac (1997)

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DOI: 10.1145/258305.258334

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/fpga/TencaE97
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  - https://dblp.org/rec/conf/fpga/TencaE97
Alexandre F. Tenca, Milos D. Ercegovac:
Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size. FPGA 1997: 159-165

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