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"A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS."

Annachiara Spagnolo et al. (2014)

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DOI: 10.1109/ESSCIRC.2014.6942025

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-02

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  - conf/esscirc/SpagnoloVDW14
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Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq:
A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. ESSCIRC 2014: 75-78

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