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"A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss ..."

U. Fat Chio et al. (2011)

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DOI: 10.1109/ESSCIRC.2011.6044982

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-29

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  dblp key:
  - conf/esscirc/ChioCCSUM11
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U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC 2011: 363-366

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