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"Built-In Generation of Weighted Test Sequences for Synchronous Sequential ..."

Irith Pomeranz, Sudhakar M. Reddy (2000)

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DOI: 10.1109/DATE.2000.840287

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/date/PomeranzR00
Irith Pomeranz, Sudhakar M. Reddy:
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. DATE 2000: 298-304

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