Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Device-conscious circuit designs for 0.5-V high-speed memory-rich ..."

Akira Kotabe et al. (2011)

> Home

Details and statistics

DOI: 10.1109/CICC.2011.6055313

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cicc/KotabeITTH11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cicc/KotabeITTH11
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi:
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC 2011: 1-7

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.