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"A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA ..."

Thibaut Stimpfling et al. (2018)

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DOI: 10.1109/CCGRID.2018.00067

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/ccgrid/StimpflingLBS18
Thibaut Stimpfling, J. M. Pierre Langlois, Normand Bélanger, Yvon Savaria:
A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis. CCGrid 2018: 402-411

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