"A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET."

Stevo Bailey et al. (2018)

Details and statistics

DOI: 10.1109/ASSCC.2018.8579326

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

a service of  Schloss Dagstuhl - Leibniz Center for Informatics