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ORCID"A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS."
Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada (2011)
- Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC 2011: 75-76
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