Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A reduced jitter-sensitivity clock generation technique for ..."

Yang Jiang et al. (2010)

> Home

Details and statistics

DOI: 10.1109/APCCAS.2010.5774943

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/apccas/JiangWCSUM10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/apccas/JiangWCSUM10
Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. APCCAS 2010: 1011-1014

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.