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"Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip ..."

Luis Castano-Londono et al. (2019)

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DOI: 10.1007/978-3-030-31019-6_5

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-09

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  dblp key:
  - conf/wea2/Castano-Londono19
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  - https://dblp.org/rec/conf/wea2/Castano-Londono19
Luis Castano-Londono, Cristian Alzate-Anzola, David Marquez-Viloria, Guillermo Gallo, Gustavo Osorio:
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool. WEA 2019: 52-63

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