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"A design for testability scheme to reduce test application time in full scan."

Dhiraj K. Pradhan, Jayashree Saxena (1992)

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DOI: 10.1109/VTEST.1992.232724

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vts/PradhanS92
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  persistent URL:
  - https://dblp.org/rec/conf/vts/PradhanS92
Dhiraj K. Pradhan, Jayashree Saxena:
A design for testability scheme to reduce test application time in full scan. VTS 1992: 55-60

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