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"A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low ..."

Wenjun Wang et al. (2008)

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DOI: 10.1109/VETECS.2008.168

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Wenjun Wang, Xiaoguang Wu, Xiaoxuan Zhu, Guixia Kang, Xiaofeng Tao:
A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder. VTC Spring 2008: 767-771

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