"FPGA design & implementation of a very-low-latency video-see-through ..."

Tao Ai (2016)

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DOI: 10.1145/3013971.3014020

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Tao Ai:
FPGA design & implementation of a very-low-latency video-see-through (VLLV) head-mount display (HMD) system for mixed reality (MR) applications. VRCAI 2016: 39-42

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