Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and ..."

Angxiao Yan et al. (2023)

> Home

Details and statistics

DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185335

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-28

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/Yan0JSTZFLC23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/Yan0JSTZFLC23
Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi:
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. VLSI Technology and Circuits 2023: 1-2

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.