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"Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit ..."

Junnosuke Suzuki et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185293

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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  dblp key:
  - conf/vlsit/SuzukiYYGOKAKCM23
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  - https://dblp.org/rec/conf/vlsit/SuzukiYYGOKAKCM23
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits 2023: 1-2

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