"1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two ..."

Yuki Okamoto et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185263

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-09

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Yuki Okamoto, Yusuke Komura, Toshiki Mizuguchi, Toshihiko Saito, Minato Ito, K. Kimura, Tatsuya Onuki, Yoshinori Ando, Hiromi Sawai, Tsutomu Murakawa, Hitoshi Kunitake, Takanori Matsuzaki, Hajime Kimura, M. Fujita, Makoto Ikeda, Shunpei Yamazaki:
1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS. VLSI Technology and Circuits 2023: 1-2

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