"A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying ..."

Jeongkyun Kim et al. (2023)

> Home

Details and statistics

DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185223

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/KimYCCLLLYDTLSB23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/KimYCCLLLYDTLSB23
Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck:
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology. VLSI Technology and Circuits 2023: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.