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"Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs."

V. Vireen et al. (2009)

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DOI: 10.1109/VLSI.DESIGN.2009.46

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/VireenVSV09
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/VireenVSV09
V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani:
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. VLSI Design 2009: 473-478

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