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"Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical ..."

Sudip Chakrabarti, Abhijit Chatterjee (1999)

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DOI: 10.1109/VLSID.1999.10000

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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Sudip Chakrabarti, Abhijit Chatterjee:
Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models. VLSI Design 1999: 518-523

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