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"Efficient Verification and Synthesis using Design Commonalities."

Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton (1998)

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DOI: 10.1109/ICVD.1998.646662

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/SwamyEB98
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/SwamyEB98
Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton:
Efficient Verification and Synthesis using Design Commonalities. VLSI Design 1998: 542-551

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