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"A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology."

Souradip Sen et al. (2021)

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DOI: 10.1109/VLSID51830.2021.00042

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

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  dblp key:
  - conf/vlsid/SenUKGGG21
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  - https://dblp.org/rec/conf/vlsid/SenUKGGG21
Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta:
A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology. VLSID 2021: 216-221

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