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"Formal Verification Using Bounded Model Checking: SAT versus Sequential ..."

Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula (2003)

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DOI: 10.1109/ICVD.2003.1183144

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  - https://dblp.org/rec/conf/vlsid/SaabAV03
Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula:
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. VLSI Design 2003: 243-248

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