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ORCID"Design of a 3-bit Booth recoded novel VLSI concurrent ..."
D. V. Poornaiah, P. V. Ananda Mohan (1995)
- D. V. Poornaiah, P. V. Ananda Mohan:
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. VLSI Design 1995: 392-397
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