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"A Partitioning and Storage Based Built-In Test Pattern Generation Method ..."

Irith Pomeranz, Sudhakar M. Reddy (2002)

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DOI: 10.1109/ASPDAC.2002.995013

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

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  - https://dblp.org/rec/conf/vlsid/PomeranzR02
Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. ASP-DAC/VLSI Design 2002: 677-682

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