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"A High-Performance and Area-Efficient VLSI Architecture for the PRESENT ..."

Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar (2018)

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DOI: 10.1109/VLSID.2018.96

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/PandeyGK18
Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar:
A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher. VLSID 2018: 392-397

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