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"Simulation Based Verification using Temporally Attributed Boolean Logic."

Subrat Kumar Panda et al. (2007)

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DOI: 10.1109/VLSID.2007.141

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/PandaRCK07
Subrat Kumar Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar:
Simulation Based Verification using Temporally Attributed Boolean Logic. VLSI Design 2007: 57-62

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