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"VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable ..."

S. K. Misra et al. (1998)

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DOI: 10.1109/ICVD.1998.646627

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, Marc S. Diamondstein:
VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay. VLSI Design 1998: 326-329

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