"FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor."

Vivek Kumar et al. (2023)

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DOI: 10.1109/VLSID57277.2023.00067

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta:
FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. VLSID 2023: 1-6

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