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"An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits."

Zbigniew Kalbarczyk et al. (1999)

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DOI: 10.1109/ICVD.1999.745158

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/KalbarczykPLI99
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/KalbarczykPLI99
Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer:
An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. VLSI Design 1999: 260-265

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