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"Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis."

Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa (1999)

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DOI: 10.1109/ICVD.1999.745140

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/JacommePB99
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/JacommePB99
Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa:
Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. VLSI Design 1999: 151-156

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