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ORCID"Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - ..."
Subhomoy Chattopadhyay, Rakesh Patel (2007)
- Subhomoy Chattopadhyay, Rakesh Patel:
Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. VLSI Design 2007: 5
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